Scribe street structure for backend interconnect semiconductor wafer integration

ABSTRACT

A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality. A separation structure that includes metal is located in the interconnect structure. At least a portion of the separation structure is located in a saw kerf of the street. The separation structure is arranged to provide a predefined separation path for separating the first die area during a singulation process.

BACKGROUND

The present disclosure relates generally to semiconductors, and moreparticularly, to a scribe street structure for backend interconnectsemiconductor wafer integration and method for forming the same.

In present metal and dielectric semiconductor wafer integration, duringa sawing operation (singulation) of the semiconductor die of a wafer,uncontrollable cracking or chipping occurs within the dielectric layersof the backend interconnect structure of the semiconductor die or withinthe bulk substrate (Si, etc) of the semiconductor die. Such cracking canpropagate into the active die area and cause immediate or latentelectrical failure of the device.

One known technique of stopping cracks in a dielectric material includesplacing one continuous barrier wall adjacent each chip and a sacrificialcomposite structure in combination therewith, between the wall and thecenter of a dicing line. The composite structure includes a means fordispersing the energy associated with crack propagation, whereby anycrack having sufficient energy to penetrate the composite structure istransformed into a plurality of weaker cracks incapable of penetratingthe barrier wall. However, such a technique has limits with respect tothe magnitude of the cracks that it can arrest, and furthermore, doesnot facilitate a predictable separation path.

In addition, the problem of delamination and crack propagation hashistorically been solved by a number of methods. One approach includedattempting to improve the adhesion strength of the materials beingsingulated. Another method included constructing a “crack stop” orbarrier that impedes crack propagation. Yet another method includedincreasing the scribe width (i.e., buffer zone) to increase the distancea crack must propagate before it becomes lethal to the device. Stillfurther, another method included reducing the singulation processthroughput, either by reducing cut speed or changing saw blades at amore frequent interval. In general, these methods fail to provide for anoptimized process.

Accordingly, it would be desirable to provide an improved semiconductormanufacturing method for overcoming the problems in the art.

SUMMARY

A method of making a semiconductor device includes forming a waferhaving a substrate and an interconnect structure over the substrate. Thewafer also includes a plurality of die areas and a scribe street locatedbetween a first die area of the plurality and a second die area of theplurality. A separation structure that includes metal is located in theinterconnect structure. At least a portion of the separation structureis located in a saw kerf of the scribe street. The separation structureis arranged to provide a predefined separation path for separating thefirst die area during a singulation process.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present disclosure are illustrated by way ofexample and not limited by the accompanying figures, in which likereferences indicate similar elements, and in which:

FIG. 1 is a top layout plan view of a scribe street having a separationstructure according to one embodiment of the present disclosure;

FIG. 2 is a side view of two adjacent columns of the separationstructure of the scribe street according to one embodiment of thepresent disclosure;

FIG. 3 is a top layout plan view of a portion of the scribe street ingreater detail according to one embodiment of the present disclosure;

FIG. 4 is a top layout plan view of a portion of the scribe streetaccording to one embodiment of the present disclosure that illustrates aseparation process;

FIG. 5 is a top layout plan view of a scribe street having a separationstructure according to another embodiment of the present disclosure; and

FIG. 6 is a top layout plan view of a scribe street having a separationstructure according to yet another embodiment of the present disclosure.

The use of the same reference symbols in different drawings indicatessimilar or identical items. Skilled artisans will also appreciate thatelements in the figures are illustrated for simplicity and clarity andhave not necessarily been drawn to scale. For example, the dimensions ofsome of the elements in the figures may be exaggerated relative to otherelements to help improve the understanding of the embodiments of thepresent invention.

DETAILED DESCRIPTION

FIG. 1 is a top layout plan view of a scribe street having a separationstructure according to one embodiment of the present disclosure.Semiconductor wafer 10 includes a plurality of die areas as indicated byreference numerals 12, 14, 16, and 18. Die areas 12, 14, 16 and 18represent active and/or functional regions of the wafer 10. Die areas12, 14, 16 and 18 are separated from one another by scribe street 20. Inone embodiment, scribe street 20 has a width dimension on the order ofapproximately 80-120 μm. In addition, each die area includes a crackstop 22 and edge seal 24. Crack stop 22 is provided for terminatingcracks that may propagate in a direction of a corresponding die. Edgeseal 24 provides a seal for protecting a corresponding die duringsingulation and/or packaging steps.

Wafer 10 can also include one or more test pads (26, 28 and 30) andother structures, for example photo alignment key 32, located within thescribe street 20. Test pads (26, 28 and 30) provide an interface forelectrical tests of various test structures for process monitoring. Thephoto alignment key 32 provides an alignment target or reference formask alignments and/or related processing steps.

During a singulation process, the various die regions of wafer 10 areseparated by cutting within the scribe street 20. The material removedduring cutting is contained within a region described as the saw bladekerf region. As shown in FIG. 1, the saw blade kerf can be of a givenwidth, such as illustrated by the arrow indicated by reference numeral34.

FIG. 1 further illustrates scribe street 20 having a plurality ofseparation structures according to one embodiment of the presentdisclosure. Separation structures are indicated, for example, byreference numerals 36, 38, 40 and 42. In particular, separationstructure 36 surrounds die area 12. Separation structure 38 surroundsdie area 14. Separation structure 40 surrounds die area 16. Similarly,separation structure 42 surrounds die area 18. Wafer 10 can furtherinclude additional die areas and additional separation structures (notshown) surrounding respective ones of the additional die areas.

With respect to the separation structures, the separation structuresinclude at least two rows of column portions to be discussed furtherherein below. Each row of the column portions is separated from anotherrow of column portions by a potential separation path. In FIG. 1, twocolumn portions of separation structure 38 are indicated by referencenumerals 44 and 46.

FIG. 2 is a side view of two adjacent column portions (44,46) of theseparation structure 38 of the scribe street 20 according to oneembodiment of the present disclosure. Prior to discussing the columnportions further, note that semiconductor wafer 10 includes a substrate48 and an interconnect structure 50 overlying the substrate 48. Theinterconnect structure 50 includes a plurality of metal interconnectlayers, vias, dielectric layers, other layers (e.g., barrier layers),etc., according to the particular requirements of a semiconductor devicemanufacturing process.

Referring again to the column portions 44 and 46, a separation path 45is disposed in between the column portions. Column portions 44 and 46form selectively reinforced structures, separated by a non-reinforcedregion. Separation path 45 lies within the non-reinforced region. Inaddition, column portions 44 and 46 can be made similarly or different.For example, column portion 46 may include one or more independentcolumns coupled together at one or more metal layers, thus creating aportion having a length different than column portion 44.

In one embodiment, column portion 44 comprises a plurality ofinterconnect layers. Interconnect layers include, for example, metal andvia layers. As shown, metal layers of column portion 44 include metal 1(M1) through metal 8 (M8) (or last metal) for the particularsemiconductor device application. Metal 1 layer includes a plurality ofmetal lines 52, 54, 56, and 58, extending perpendicular to the surfaceof and into the drawing figure. Metal 2 layer includes a plurality ofmetal lines, in a plane above the plane of metal 1, and orientedperpendicular to the metal lines of metal 1. For example, metal 2includes metal line 60, extending left to right. Interconnectingadjacent metal layers of column portion 44 are vias 62. As shown, afirst metal layer includes metal lines oriented in a first direction anda second metal layer overlying the first metal layer and having metallines oriented in a second direction, the second direction beingperpendicular to the first direction. The metal lines of the first metallayer couple to the metal lines of the second metal layer using vias.

In addition, the use of metal lines (versus solid metal regions) incolumn portion 44 is determined in part by the design rules of theparticular semiconductor device manufacturing process being used toconstruct semiconductor devices with the various embodiments of theseparation structure of the present disclosure. Alternatively, if designrules of a given semiconductor device manufacturing process permit, thefirst metal layer could include a solid metal area having a metaldensity up to one hundred percent (100%) and the second metal layercould include a similar solid metal area, the first metal layer beingcoupled to the second metal layer using vias. Alternatively, the secondmetal layer could include an area different from a solid metal area. Asused herein, metal density includes a percentage of metal by area in agiven layer.

FIG. 3 is a top layout plan view of a portion of the scribe street 20 ingreater detail according to one embodiment of the present disclosure. Inparticular, separation structure 38 comprises two adjacent rows ofcolumn portions of selectively reinforced structures separated by anon-reinforced region. Separation path lies within the non-reinforcedregion. As shown, the column portions of a first row are aligned withcolumn portions of the second row, for example, column portion 44 is inalignment with column portion 46. In addition, the metal lines of a topmost layer of column portion 44 are oriented perpendicularly withrespect to metal lines of a top most layer of column portion 46. Withina single row of column portions, metal lines of a top most layer ofadjacent column portions of the selectively reinforced structures areoriented perpendicular to one another. Still further, note that aportion of saw blade kerf 34 falls within the row of column portionsincluding column portion 44. Upon an interaction of a saw blade with therow of column portions (i.e., the one containing column portion 44) ofseparation structure 38, a separation preferentially propagates alongthe separation path 45.

FIG. 4 is a top layout plan view of a portion of the scribe street 20according to one embodiment of the present disclosure that illustrates aseparation process along the separation path 45. During the singulationoperation, a saw blade 64 is advanced across the wafer 10 within thescribe street 20 in a direction indicated by the arrow 66. As the sawblade 64 cuts into the row of column portions of the separationstructure 38, and in particular, the one containing column portion 44,separation preferentially propagates along the separation path 45. Sucha preferential propagation of the separation results from an interactionof the saw with the row of column portions and the presence of anon-reinforced region between adjacent rows of the column portions ofthe separation structure 38.

FIG. 5 is a top layout plan view of a scribe street 20 having aseparation structure 72 according to another embodiment of the presentdisclosure. Separation structure 72 is similar to the separationstructure 38 discussed herein above, with the following differences.Separation structure 72 includes a first row of column portions and asecond row of column portions, wherein the column portions of the firstrow are in a staggered arrangement with respect to the column portionsof the second row. For example, column portion 74 is in a staggeredalignment with respect to column portion 76. In other words, the columnportions of the first row are offset from a corresponding column portionof the second row by an amount less than the width of an individualcolumn portion. In addition, separation path 75 occurs within a regionbetween the first and second rows of column portions.

FIG. 6 is a top layout plan view of a scribe street 20 having aseparation structure according to yet another embodiment of the presentdisclosure. The separation structure is similar to the separationstructure 38 discussed herein above, with the following differences. Theseparation structure of FIG. 6 includes a plurality of rows of columnportions spanning across the scribe street 20. For example, several ofthe rows of column portions are indicated by reference numerals 82, 84,and 86. Potential separation paths between adjacent rows of columnportions of the separation structure are indicated by reference numeral88. Furthermore, as shown, the column portions of a first row are in analigned arrangement with respect to the column portions of a second row.Alternatively, the column portions of a first row can be arranged in astaggered alignment with respect to column portions of a second row.

The embodiments of the present disclosure advantageously providespecially designed separation structures to substantially eliminateuncontrollable cracking or chipping within the dielectric layers or bulksubstrate (Si, etc) of the semiconductor die during a singulationoperation. Accordingly, during singulation, the likelihood that crackingcan propagate into the active die area and cause immediate or latentelectrical failure of the device is substantially reduced, if noteliminated. The present embodiments further allow for a reduction inscribe street width for wafers incorporating low-k dielectrics in theback end interconnect structure. As used herein, low-k refers todielectrics having a value under 3.50.

As discussed herein, the structures in the embodiments of the presentdisclosure comprise discontinuous metal lines separated by spaces ofdielectric to facilitate preferential removal. That is, the metalfeatures are preferentially delaminated and removed as part of the sawkerf, as opposed to functioning as a crack stop or energy dissipatingstructure. In one embodiment, the discontinuous metal lines, separatedby dielectric, alternate in their respective orientations relative to adie edge. Furthermore, the structures of the present embodiments are notintended to remain intact, but rather are intended to be preferentiallyremoved in the wafer sawing process. Accordingly, the separationstructure breaks up into manageable pieces of the discontinuous metallines.

In one embodiment of the present disclosure, specially designed scribestreet structures are utilized to control delamination of Copper low-k(low dielectric constant) films or layers. These specially designedscribe street structures will either prevent or terminate propagation ofinter-layer cracks initiated by the sawing (or singulation) process. Theseparation structure further incorporates weak sub-structures orcomponents that preferentially fail during the singulation process. Inone embodiment, the structures comprise stacks of short metal lineslayered orthogonally and separated by a vertical dielectric interface.The vertical dielectric interface takes advantage of the weak mechanicalstrength in order to preferentially guide failure along the edges of thesaw kerf, thereby providing for a predictable damage during the sawingoperation.

The embodiments of the present disclosure differ from prior methods inthat the embodiments intentionally introduce a weak structure that failspreferentially over adjacent structures. This structure is removedduring the singulation process and produces a predictable, controlledfailure mechanism, thereby eliminating the need for “buffer zones.” Inother words, the separation structure comprises a weak zone within tworeinforced zones.

In one embodiment, the method and separation structure can be used inany copper (Cu) low-k wafer integration. The method and separationstructure could also be extended to any semiconductor wafer technology.

In the foregoing specification, the disclosure has been described withreference to various embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present embodiments as set forthin the claims below. Accordingly, the specification and figures are tobe regarded in an illustrative rather than a restrictive sense, and allsuch modifications are intended to be included within the scope of thepresent embodiments.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the term“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

1. A semiconductor wafer comprising: a substrate; an interconnectstructure located over the substrate; a plurality of die areas; a streetlocated between a first die area of the plurality and a second die areaof the plurality; a separation structure, the separation structureincludes metal located in the interconnect structure, at least a portionof the separation structure is located in a saw kerf of the street,wherein the separation structure is arranged to provide a separationpath for separating the first die area during a singulation process. 2.The semiconductor wafer of claim 1 wherein the separation structureincludes metal in the saw kerf and metal outside of the saw kerf,wherein the metal outside the saw kerf is predisposed to separate fromthe first die area during a sawing process.
 3. The semiconductor waferof claim 1 wherein: the separation structure includes a plurality ofindependent metal structures including metal in the interconnectstructure, wherein at least a portion of each metal structure of theplurality is located in the saw kerf, wherein the plurality ofindependent metal structures are arranged to provide the separationpath.
 4. The semiconductor wafer of claim 3 wherein each of the metalstructures of the plurality includes a plurality of metal lines locatedin an interconnect layer of the interconnect structure.
 5. Thesemiconductor wafer of claim 4 wherein for each of the metal structuresof the plurality, the plurality of metal lines are oriented generallyparallel to each other.
 6. The semiconductor wafer of claim 4 whereineach of the metal structures of the plurality includes a secondplurality of metal lines located in a second interconnect layer of theinterconnect structure.
 7. The semiconductor wafer of claim 6 whereinfor each metal structure of the plurality, the metal lines of the secondplurality are physically coupled by metal to the metal lines of thefirst plurality.
 8. The semiconductor wafer of claim 6 wherein for eachmetal structure of the plurality: each of the plurality of metal linesis oriented generally parallel to each other; each of the secondplurality of metal lines is oriented generally orthogonal to theplurality of metal lines.
 9. The semiconductor wafer of claim 8 whereineach metal structure of the plurality further comprises: a thirdplurality of metal lines located in a third interconnect layer of theinterconnect structure, the third plurality of metal lines are orientedgenerally parallel to each other and generally parallel to the metallines of the plurality of the metal structure; a fourth plurality ofmetal lines located in a fourth interconnect layer of the interconnectstructure, the fourth plurality of metal lines are oriented generallyparallel to each other and generally parallel to the metal lines of thesecond plurality of the metal structure.
 10. The semiconductor wafer ofclaim 9 wherein the interconnect layer is located above the secondinterconnect layer, the second interconnect layer is located above thethird interconnect layer, and the third interconnect layer is locatedabove the fourth interconnect layer.
 11. The semiconductor wafer ofclaim 9 wherein for each metal structure of the plurality, the pluralityof metal lines, the second plurality of metal lines, the third pluralityof metal lines, and the fourth plurality of metal lines are each coupledby metal to each other.
 12. The semiconductor wafer of claim 1 furthercomprising dielectric material located along the separation path in theinterconnect structure.
 13. The semiconductor wafer of claim 1 whereinthe separation structure includes a first plurality of metal structureslocated on a first side of the separation path and at least one metalstructure located on a second side of the separation path, the firstplurality of metal structures are independent of the at least one metalstructure.
 14. The semiconductor wafer of claim 13 wherein theseparation path includes dielectric material located in the interconnectstructure, the dielectric material is located between the firstplurality of metal structures and the at least one metal structure. 15.The semiconductor wafer of claim 14 wherein the dielectric material ischaracterized as a low K dielectric material.
 16. The semiconductorstructure of claim 13 wherein at least a portion each of the firstplurality of metal structures is located in the saw kerf and wherein theat least one metal structure is located outside of the saw kerf.
 17. Thesemiconductor wafer of claim 1 further comprising: a first crack stoplocated in the first die area; a second crack stop located in the seconddie area, wherein the separation structure is located between the firstcrack stop and the second crack stop.
 18. The semiconductor wafer ofclaim 17 further comprising: a first edge seal located on a die side ofthe first crack stop; a second edge seal located on a die side of thesecond crack stop.
 19. The semiconductor wafer of claim 1 wherein: theseparation structure includes a plurality of metal structures includingmetal in the interconnect structure, wherein at least a portion of eachmetal structure of the plurality is located in the saw kerf, wherein theplurality of metal structures are arranged to provide the separationpath.
 20. The semiconductor structure of claim 19 wherein the pluralityof metal structures are arranged in a row in the street.
 21. Thesemiconductor wafer of claim 19 wherein each metal structure of theplurality is designed to be entirely removed during a sawing processesif at least a part of the structure is contacted by the saw.
 22. Thesemiconductor wafer of claim 1 wherein the metal includes copper.
 23. Asemiconductor wafer comprising: a substrate; an interconnect structurelocated over the substrate; a plurality of die areas, the plurality ofdie areas separated a plurality of intersecting streets; each die areais surrounded by a separation structure including metal in theinterconnect structure with at least a portion of the metal located in asaw kerf; wherein the separation structure is predisposed to separatealong a separation path during a sawing process.
 24. The semiconductorwafer of claim 23 wherein the separation structure surrounding each diearea includes a plurality of metal structures surrounding each die area,wherein each of the plurality of metal structures includes metal locatedin the interconnect structure, at least a portion of each metalstructure of the plurality is located in a saw kerf.
 25. Thesemiconductor wafer of claim 24 wherein each of the plurality of metalstructures includes a first plurality of metal lines of a firstinterconnect layer of the interconnect structure and a second pluralityof metal lines of a second interconnect layer of the interconnectstructure, wherein for each of the plurality of metal structures, thefirst plurality of metal lines are generally parallel to each other andthe second plurality of metal lines are generally orthogonal to thefirst plurality of metal lines, the first interconnect layer is locatedover the second interconnect layer.
 26. The semiconductor wafer of claim25 wherein for each of the plurality of metal structures, the firstplurality of metal lines is coupled with metal to second plurality ofmetal lines.
 27. The semiconductor wafer of claim 23 further comprising:dielectric material located along the saw path in the interconnectstructure.
 28. A method of forming a semiconductor device, the methodcomprising: forming a wafer with a substrate and interconnect structureover the substrate, the wafer including a plurality of die areas, thewafer further including a street located between a first die area of theplurality and a second die area of the plurality, the wafer including aseparation structure, the separation structure includes metal located inthe interconnect structure, at least a portion of the separationstructure is located in a saw kerf of the street, wherein the separationstructure is arranged to provide a separation path for separating thefirst die area during a singulation process.
 29. The method claim 28further comprising: singulating the plurality of die areas, wherein thesingulating includes sawing along the saw kerf, wherein an edge of asingulated die is formed along the separation path during thesingulating.
 30. The method of claim 28 wherein the separating structureincludes a plurality of independent metal structures including metal inthe interconnect structure, wherein at least a portion of eachindependent metal structure of the plurality is located in the saw kerf,wherein the plurality of independent metal structures are arranged toprovide the separation path.
 31. The method of claim 30 wherein: each ofthe metal structures of the plurality includes a first plurality ofmetal lines located in a first interconnect layer of the interconnectstructure; each of the metal structures of the plurality includes asecond plurality of metal lines located in a second interconnect layerof the interconnect structure; for each metal structure of theplurality, each of the first plurality of metal lines is orientedgenerally parallel to each other; for each metal structure of theplurality, each of the second plurality of metal lines is orientedgenerally orthogonal to the metal lines of the first plurality.
 32. Asemiconductor wafer comprising: a plurality of die areas; a streetlocated between a first die area of the plurality and a second die areaof the plurality; means for providing a separation path for singulatingthe first die area, the means includes metal in a saw kerf and metaloutside of the saw kerf, wherein the metal outside the saw kerf ispredisposed to separate from the first die area during a sawing process.33. The semiconductor wafer of claim 32 wherein the metal outside thesaw kerf is located on a street side of the separation path.
 34. Asemiconductor wafer comprising: a substrate; a plurality of die areasoverlying the substrate; a scribe street located between a first diearea and a second die area of the plurality of die areas; and aseparation structure located within the scribe street, the separationstructure including reinforced regions separated by non-reinforcedregions, the non-reinforced regions defining at least one separationpath, wherein responsive to a singulation of the first die area from thesecond die area, at least one of the reinforced regions of theseparation structure is preferentially removed along the separationpath.
 35. The semiconductor wafer of claim 34 wherein the reinforcedregions of the separation structure comprises at least two rows ofcolumn portions and wherein a non-reinforced region is disposed inbetween the at least two rows of column portions.
 36. The semiconductorwafer of claim 35 wherein the column portions comprise selectivelyreinforced structures.
 37. The semiconductor wafer of claim 36 whereinthe selectively reinforced structures comprise a plurality ofinterconnect layers including metal layers and vias.
 38. Thesemiconductor wafer of claim 37 wherein a first metal layer includesmetal lines oriented in a first direction and a second metal layeroverlying the first layer includes metal lines oriented in a seconddirection, the second direction being substantially perpendicular to thefirst direction, and wherein the metal lines of the first metal layercouple to the metal lines of the second metal layer using vias.
 39. Thesemiconductor wafer of claim 34 wherein the non-reinforced regionscomprise vertical dielectric interfaces, wherein at least one of thevertical dielectric interfaces provides a path of weak mechanicalstrength in order to preferentially guide a failure along an edge of asaw kerf during singulation.
 40. The semiconductor wafer of claim 34wherein the reinforced regions comprise discontinuous stacks of metallines, the metal lines of a stack being layered orthogonally, andwherein the non-reinforced regions comprise vertical dielectricinterfaces.